Flexible Clock IC Architectures

Due to the wide diversity of frequency and clock jitter requirements of the reference

clocks required in modern electronic systems, an assortment of standalone crystal oscillators and fixed-frequency clock multiplier ICs are typically required to provide a complete timing architecture for both the data path and control plane. The Si5338 is the industry's first clock generator capable of supporting any-rate frequency synthesis on four independent output clocks. By providing this level of frequency flexibility, the Si5338 eliminates the need for fixed-frequency clock generators and discrete crystal oscillators.

Modern communication, networking, and broadcast video hardware designs use a wide variety of processors, FPGAs, memory, and physical layer transceivers to perform all of the tasks and processes required by end applications. The timing architecture in these applications is becoming increasingly complex due to the growing level of integration required in new designs. Each IC has its own unique reference clock requirements and multiple clock domains must be carefully managed in a single design. Further complicating hardware design, high-speed physical layer transceivers and FPGAs with embedded serializer/deserializers (SERDES) have stringent jitter requirements to ensure compliance with the end applications' bit-error rate (BER) specifications.

Given the unique requirements of each hardware design, the timing architecture is typically customized for each application using a combination of fixed-frequency clock generators/multipliers, discrete crystal oscillators, and muxes. Additional level translator ICs are necessary when clock format translation is required between the clock generator and the IC. Some applications require multi-protocol high-speed serial data transmission, These applications require multiple oscillators and supporting mux circuitry to support the application's multi-protocol requirements.

In addition to generating nominal clock frequencies, some applications require frequency-margined clocks that produce references that are at a slight positive or negative offset to the nominal frequency (e.g., 66.6 MHz 5%). These frequency-margined clocks are used during product validation and/or manufacturing test to test the robustness of the design over voltage and temperature and ensure sufficient setup and hold margin for the critical components in the system. Traditionally, frequency margining has been implemented using discrete custom frequency crystal oscillator. Since these additional components are exclusively used during product validation and/or manufacturing test and not during normal operation, BOM cost and complexity are increased to support this requirement

Flexible Clock IC Architectures

By: Chris Bartik

POST COMMENT

Brake rotors - what happens when you press the brake pedal At Least These Lobsters Show They've Got a Spine Эстонское Гражданство И Эстонский Паспорт John White Miller Place How to Find a Good Accident Claim Specialist Cigars Cigars Cigars Кованые Перила Historia Breve Sobre La Retroexcavadora How The Humble Hedgehog Can Make You Great (And Rich!) When Will See How Stupid He's Being By Having An Affair? CAD - the best tool for GIS Пикеты Для Просвещения И Против Злоупотреблений В Психиатрии В Рф Anorexia Mirabilis in the Middle Ages