Fundamentals Of Parametric Testing Of Phase Change Memory
A PCM cell is a tiny chunk of a chalcogenide alloy that can be switched rapidly from
an ordered crystalline phase (with low resistance) to a disordered, amorphous phase (with much higher resistance) through the focused application of heat in the form of an electrical pulse. These same materials are also widely used in the active layers of re-writable optical media such as CDs and DVDs. The switch from the crystalline to the amorphous phase and back is triggered by melting and quick cooling (or a slightly slower process known as re-crystallization). According to Keithley Instruments, www.keithley.com , one of the most promising PCM materials is GST (germanium, antimony, and tellurium), which has a melting temperature in the range of 500600C.
Amorphous state vs. the crystalline state. The differing levels of resistivity of the crystalline and amorphous phases of these alloys allow them to store binary data. The high resistance amorphous state is used to represent a binary 0; the low resistance crystalline state represents a 1. The newest PCM designs and materials can achieve multiple distinct levels [1], for example, 16 crystalline states, not just two, and each with different electrical properties. This allows a single cell to represent multiple bits, and to increase memory density substantially.
In the amorphous phase, the GST material has short-range atomic order and low free electron density, which results in higher resistivity. This is sometimes referred to as the RESET phase, because it is usually formed after a RESET operation, in which the temperature of the PCM device under test (DUT) is raised slightly above the melting point, then the GST is suddenly quenched to cool it. The rate of cooling is critical for the formation of the amorphous layer. The typical resistance of the amorphous layer can exceed one mega-ohm.
In the crystalline phase, the GST material has long-range atomic order and high free electronic density, which results in lower resistivity. This is also known as the SET phase because it is formed after a SET operation, in which the temperature of the material is raised above the re-crystallization temperature but below the melting point, then cooled slightly slower to allow crystalline grains to form throughout the layer. The typical resistance of the crystalline phase ranges from 1 to 10 kilo-ohms. The crystalline phase is a low energy state; therefore, when heat is applied to material in the amorphous phase and the temperature approaches the crystallization temperature, it tends to change spontaneously to the crystalline phase.
The structure of a typical GST PCM device has a resistor attached to the underside of the GST layer that acts as a heating element. Electrical current though it causes localized heating/melting that affects only a small area around the tip of the resistor. Erase/RESET pulses set high resistance or logical 0 and form an amorphous layer area on the device. Erase/RESET pulses are higher, narrower, and steeper than Write/SET pulses. A SET pulse, which sets a logical 1, re-crystallizes the amorphous layer back to the crystalline state.
Pulse requirements for PCM device characterization. The voltage and current values of the RESET and SET pulses used should be carefully selected to produce melting and re-crystallization. RESET pulses should raise the temperature just above the melting point and then allow the material to cool rapidly to the amorphous phase. SET pulses should raise the temperature just above the re-crystallization temperature but below the melting point, and allow a longer time to cool it; therefore, the pulse width and fall time for a SET pulse should be longer than for a RESET pulse.
In functional testing, pulse widths of one microsecond or shorter are usually sufficient. A pulse of this duration will produce enough energy either to melt PCM material or to re-crystallize it. Pulse voltages need to be as high as 6V, and its desirable for them to be higher, to reach melting temperatures. Current values range from 0.33mA.
Fall time for a RESET pulse is a critical parameter [2]. The state of the PCM technology determines the required minimum for a fall time. Currently, it is a common requirement to have 3050 nanoseconds. Newer materials will push that requirement to shorter fall times. If the pulse fall time is longer than that required time, the material may not effectively quench into an amorphous phase.
Critical parameters for PCM device characterization and materials research. The ability to develop new PCM materials and refine device designs depends largely on manufacturers abilities to characterize several parameters:
Re-crystallization rate Current re-crystallization rates are now as short as several tens of nanoseconds, but they may soon drop to as little as a few nanoseconds. That will make reducing the time needed to make a measurement increasingly crucial.
Data retention As discussed previously, the SET phase is a lower energy state, and PCM materials tend to re-crystallize spontaneously. The rate of crystallization is temperature dependent. Therefore, data retention can be defined as a maximum temperature at which data, the RESET state, will remain unchanged and stable for a specified time period (typically 10 years).
Cycling endurance This is a measurement of how many times a memory cell can be successfully programmed to the 0 and 1 states. The newer multi-state memory cells with additional distinct states mentioned previously allow packing more memory into a single cell, which modifies cycling endurance test procedures.
Drift This is simply a measure of the drift of the cells resistance over time, typically performed at various temperatures [3].
Read Disturb This is an evaluation of how the read procedure impacts the stored state. The measurement pulse must be less than 0.5V. Higher voltages will lead to Read Disturb problems.
Resistance-current (RI) curves The RI curve is one of the most common parameters collected during PCM characterization. A pulse sequence is sent through a DUT. The first one, a RESET pulse, sets the resistance of the DUT to the high value. It is followed by a DC-read or MEASURE pulse thats usually 0.5V or lower in order to avoid affecting the state of the DUT. This is followed by a SET pulse and another MEASURE pulse. The entire sequence is repeated multiple times, with the amplitude of the SET pulse slowly increased to the value of the RESET pulse. RESET values slightly exceed 1M; SET resistance values range from one mega-ohm to several kilo-ohms, depending on the value of the SET current.
I-V (current-voltage) curves To generate these curves, the starting point is a DUT that was previously RESET to its highly resistive state. Then voltage applied to the DUT is swept from low to high values. The dynamic switch from a high- to low-resistive state in the presence of a load resistor produces a characteristic RI curve with a snapback, an area of negative resistance. Snapback itself is not a feature of PCMs or of PCM testing, but rather a side effect of the R-load technique that has long been used to obtain both RI and I-V curves.
In the standard R-Load measurement technique a resistor is connected in series with the DUT, allowing current to be measured across the DUT by measuring the voltage across the load resistor. Active, high impedance probes and an oscilloscope are used to record the voltage across the load resistor. Current across the DUT will be equal to the applied voltage (VAPPLIED) minus the voltage across the device (VDEV), divided by the load resistance. The values of the load resistor usually range from one to three kilo-ohms. This technique involves a tradeoff: if the load resistance is too high, RC effects and the voltage division between the R-Load and the DUT limits this techniques performance; however, if the resistor value is too small, it impacts the current resolution.
A New Measurement Technique. Recently, a new current-limiting technique has been developed that eliminates the need for the load resistor. Tight control over the level of current sourced allows for more accurate characterization of low currents in the RI curve. This new pulse mode technique, which allows taking both I-V and RI curves in a single sweep, employs a high-speed pulse source and measure instrument: the Keithley dual-channel Model 4225-PMU Ultra-Fast I-V Module installed in a Model 4200-SCS Semiconductor Characterization System. The new module can source voltage pulses and simultaneously measure both voltage and current responses with high accuracy, with rise and fall times as short as 20ns.
The elimination of the load resistor also eliminates the snapback side effect. The Model 4225-PMU, and the Model 4225-RPM Remote Amplifier/Switches that extend its sensitivity, are tightly integrate with the Model 4200-SCS parametric tester, which not only provides the other measurement functions necessary to characterize a PCM device but also offers the ability to automate the entire testing process.
Conclusion. As industry looks for more reliable memory devices, the ability to characterize these new devices quickly and accurately during development becomes increasingly important. New tools and techniques now being developed will be critical to this pursuit.
by: Alexander Pronin
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