JTAG gets an update for silicon instruments

JTAG gets an update for silicon instruments

What do the acronyms NTF and NFF mean? No trouble found and no fault found. And they're the least desirableacronyms to hear when you are an IC vendor trying to understand afailure in a customer system. Customer says your IC is not working, it is removed from the system, its run on IC ATE and it passes all tests. No failure found. If only the tests could be run when the IC was on the customers PCB. The slide below illustrates the challenge of correlating in-system failures with ATE tests due to the environmental differences.

What is needed is a low-pin contact approach to run tests in-system and a unified architecture for enabling in-situ test of ICs.Test re-use from simulation, through first silicon, IC ATE and board/system test using a common language for validation and test across the IC life-cycle results in the least amount of engineering time. This means abandoning the current verilog test bench for JTAGsimulation, then STIL for ATE and SVF for board test approaches. For production test, higher-bandwidth interfaces on the IC can be used rather than JTAG, but each test should also be enabled through the low speed bandwidth of IEEE 1149.1.

Chair CJ Clark has championed three new instructions in the IEEE 1149.1 working group, which enable in-situ (in-system) use of silicon instruments. CLAMP_HOLD/CLAMP_RELEASE is a new non-intrusive way of holding the IC pins during operation of silicon instruments. It's been designed such that no extra routing around the boundary is required by the designer. This instruction operates on a new test-mode persistence controller so the I/O may remain stable across private and design specific instructions accessing the instruments. The third instruction is IC_RESET which enable on-chip control via JTAG of the reset# or POR# pins. It prevents reset pins from inadvertent toggle via the system during silicon instrument operation. It enables critical system resets between instrument operation without power-down or additional pin access.

There are two more instructions the group has finalized on, INIT_SETUP and INIT_RUN. These address the need for conditioning complex I/Os prior to test modes such as setting voltage levels, differential swing, SERDES protocols and common mode voltages.

The P1149.1-2011 Working Group has defined a re-useable language PDL and BSDL extensions for internal JTAG. The original article by CJ Clark withfigures anddiagrams can be found in Intellitech's newsletter at JTAG/IJTAG Intellitech Newsletter. Free software is available to try some of the new features of IEEE 1149.1/JTAG at IJTAG NEBULA Software

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