Mcu And Fpga-based Digital Storage Oscilloscope Simple Design - The Electronics Industry

L Introduction With traditional analog Oscilloscopes Compared

. Digital Storage Oscilloscope Not only can be stored waveform, small size, low power consumption and easy use, but also has powerful real-time signal processing analysis. In the field of electronic measurement, digital storage oscilloscope is gradually replacing analog oscilloscope. However, China using high-performance digital storage oscilloscopes rely mainly on foreign products, but also expensive. So the research has important value digital storage oscilloscope. By this, a simple design of digital storage oscilloscope, tested and excellent performance.

2 basic principle of digital storage oscilloscope

Digital storage oscilloscope with the analog signal into the oscilloscope oscilloscope difference is that immediately after the high-speed A / D converter sampling the analog signal front-end quickly, store their digital signal. And use of digital signal processing technology for real-time data stored fast processing, waveform and its parameters obtained by the oscilloscope display, which features analog oscilloscope, and high precision. Can store the signal, thus, digital storage oscilloscope can store and call the show a specific time signal.

3 System Demonstration 3.1 A / D Real-Time Sampling

According to Nyquist sampling theorem, the sampling rate must be higher than 2 times the highest frequency signal components. For sinusoidal signals, during the week there should be two sampling points. In order to restore the measured signal is not distorted, usually during the week need to sample more than 8 points. In order to meet the high-speed ADC, using FPGA control M / D converter sampling rate, in order to achieve high-speed real-time sampling. Real-time sampling allows sampling the band at full speed, the system selected ADI's 12-bit high speed A / D converter AD9220, the maximum sampling rate up to 10MHz.

3.2 Double-trace display The dual track system design based on high-speed switching analog display module Switch Gated sampling circuit into two signals, two-way waveform is stored in a memory with odd and even address bits. Dual trace display, scan address data bit odd, and then scan even address data bit. Analog Switch Instead of an ADC, to avoid the two high-speed A / D converter mutual interference, reduced system debugging difficult, and the system functions.

3.3 trigger Use FPGA internal software trigger, trigger level set by software, the Schmitt trigger parameter set easily modified to inhibit the comparator glitch. When the sample is greater than trigger level, then create a trigger. The method makes full use of FPGA resources, reduce the external circuit, eliminating the interference generated hardware glitch, easy to adjust the trigger voltage.

3.4 Regulation of the waveform display position

3.4.1 Line Scan regulation

By controlling the FPGA internal dual-port RAM (1KB) of the starting address offset to control the waveform to determine the movement. The specific method is to slide rheostat R on the level is converted to digital signals by analog transmission to the FPGA, then the initial level digital signal (reset when the display position, sliding rheostat R, level sample values) compared determine the starting address ADR0 offsets. The method can be easily implemented and automatic full screen waveform display.

3.4.2 Regulation of Row

MAXl97 sample A, B channel Position Potentiometers Value, the value obtained by the FPGA samples sent to the 16-bit serial D / A converter, MAX542 generated DC level, the DC level and column sum sent to the analog oscilloscope scan waveform display, waveform up or down to achieve. For the separation of A, B channel, the time when A-channel waveform data, FPGA must be sent PositionA potentiometer value D / A converter; while reading the B-channel waveform data, it must be sent PositionB potentiometer value D / A converter, it can adjust a potentiometer, the realization of the corresponding channel wave move up and down.

3.5 waveform data storage Digital oscilloscope waveform data storage can use an external dual-port static RAM, or general-purpose RAM, while FPGA can control the RAM address lines, thereby achieving waveform data storage. Dual-port RAM can be simultaneously read and write operations, as the system design using FPGA, so make full use of FPGA logic array and embedded array, dual-port RAM can be written to the internal FPGA, eliminating the need for external RAM, to reduce hardware, improve the reliability of simple digital oscilloscope.

4 system design The system block diagram shown in Figure 1. The whole system is based on FPGA core, including the front-end analog signal processing modules, single chip module, display module and keyboard module. The signal processing module also includes pre-class shot-class follower, programmable amplifier, shaping circuit. A, B channel signal processing by the former class into O ~ 4V, AD9220 its sampling. Waveform sample storage control module to write data to FPGA internal RAM, then the waveform display control module to display. FPGA programming set to achieve by measuring frequency, keyboard scanning, display drivers, waveform memory control functions. MCU AT89S52 control the keyboard and the whole system Lattice LCD module for human-computer interaction. Panel buttons can be easily adjusted by the waveform display.

5 hardware design 5.1 Programmable Amplifier Analog switches CD4051, broadband operational amplifier AD844 and Precision Potentiometer 10mV/div ~ 2V/div vertical resolution of multi-file. FPGA module with channel select register, write the channel number through the MCU to control the analog switch strobe different feedback resistor, to achieve different magnification, the signal conditioning to meet the AD9220 in the range of 0 ~ 4V, the specific circuit shown in Figure 2 .

5.2 Data Acquisition Module The system uses ADI's AD9220 high-speed ADCs to achieve waveform signal acquisition, AD9220 maximum sampling rate up to 10MHz, with an external crystal Oscillator 8MHz, FPGA realization of internal waveform memory by sampling. AD9220 has two DC-coupled and AC-coupled input. This system uses DC-coupled, 0 ~ 5V input mode. Using the internal 2.5V reference voltage. Because the system only 255 vertical resolution, so it's high 8-bit AD9220. Data acquisition circuit shown in Figure 3.

5.3 FPGA Design System uses VerilogHDL language software in QuartusII conducted under the FPGA logic description of programming flexibility and control circuitry required to achieve the system module.

5.3.1 Trigger Module

Single chip FPGA module is written first to set the trigger voltage, FPGA internal comparison

by:gaga

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