subject: New DSP Enhanced PLL Architecture [print this page] New DSP Enhanced PLL Architecture New DSP Enhanced PLL Architecture
Fine skew control allows adjustment of the input-to-output clock phase in picosecond increments, and digital bandwidth control allows static or dynamic modification of the PLL loop bandwidth in order to enhance PLL locking behavior and increase filtering of incoming clock jitter. These new DSP-based PLLs enable radical modifications in the system timing architecture for line cards providing multi-rate, multi-protocol support and also enabling improved test capability.
