subject: The interface of the PSP's TFT - LCD module to an FPGA [print this page] The interface of the PSP's TFT - LCD module to an FPGA
Clock
According to the data in paragraph (1) Timing characteristics of the table, in the TFT - LCD module should be driven by the clock signal, although there is a 7.83MHz and 9.26MHz to any value between the typical frequency is sufficient 9.00MHz. It is very expensive, if not impossible, create the crystal oscillator output frequency accuracy 9.00MHz. This is due to manufacturing tolerances, operating temperature and other parameters change over time. Therefore, in the TFT - LCD displaymodule provides the status of a lot of room for maneuver clock frequency can be used.
This is a screen for the driver (eg: A FPGA demo board) of the source of great advantage may not have 9MHz oscillator. On the contrary, 9MHz clock frequency may have been not directly from a multiple of 9. For example, if an FPGA prototype board with only 80MHz clock input frequency, how you will obtain the necessary clock signals to drive the TFT - LCD module, making the clock frequency range of TFT - LCM specification for that? If there is no internal PLL in FPGA?
Some of the specifications (Fox Exchange - HC736R - 27) of the 27MHz oscillator in Figure 2, the first component. It has a frequency stability of the value with the specified parameters (1) -25 ppm (parts per million). This tells us that there is a 27MHz oscillator output frequency anywhere between - 25Hz and 25Hz instead of 27MHz to 27MHz accurate.
Some manufactures also shows the value of aging, parameters (2) in Figure 2, for example, it must also be taken into account when considering changes to the oscillator output frequency is 5Hz. Are really only in this, however, all the parameters, the frequency can change, must be accurate accounting of the critical applications. For the driving TFT - LCD module, we should use a device, about the purpose of 9MHz. We should not need to worry about any deviations or changes in the frequency, as long as the time available to generate specifications.
Clock signal for up to the falling edge of the TFT - LCD display Module RGB data and synchronization signals. For the purposes of this article, we will get to use any clock frequency, there is a 9.00 MHz frequency theory relevant calculation accuracy. This immediately tells us that the image of the clock cycle 111.11ns, we read on the screen fragments, then the memory chips should have a less than 111.11 ns data access time.
Because modern memory chip SRAM and SDRAM devices for fast access time, access time in memory demand, at least not so strict and standard ready-made ready-made memory should be sufficient, if used as a video frame storage.
Timing characteristics of the clock also provides that it should be 40% to 60% duty cycle, but usually should be 50%. A clock, a 50% duty cycle is considered to be in a logic level of '1 'half of the time, and in the 0 logic level' the other half of the time. Similarly, a 30% clock duty cycle is considered to be in a logic level of '1 '30% of the time, and in the logic level 0 ', the remaining 70% of the time.
