subject: DSP chips with boundary scan test digital circuit board applications - chip, DSP-electronics industry [print this page] DSP chips with boundary scan test digital circuit board applications - chip, DSP-electronics industry
Chip Figures Board Applications are very broad. Basic support IEEE1149.1 standard DSP chips, and circuit board formed a boundary scan chain, to support boundary scan testing.
In the DSP circuit board in such a class IC They are non-boundary scan devices in the circuit board edge Connector And formed by the DSP chip boundary scan chain between. This part of the device functional test difficult. First, the DSP board with an independent timing, we can not separate the external interface by using the traditional method of input test vectors to test; Second, boundary-scan test can only be connected with the DSP chip interconnection pin test short-circuit fault can be detected, but difficult to functional tests.
This paper, boundary-scan test technology with the combination of traditional testing methods for functional testing of these devices provides a new choice. A test method
In IEEE1149.1 standard, providing four mandatory instructions: bypass instruction (BYPASS), sampling instructions (SAMPLE), pre-installed command (PRELOAD), interconnect test instruction (EXTEST). Interconnect testing according to the sampling instructions and directives of the working principle of the use of boundary scan cells can capture and drive pin signals. Using this feature of boundary-scan device can be achieved with a DSP chip on the circuit board as shown in Figure 1 Central African boundary-scan devices send a signal acquisition and incentive vector to the boundary-scan test technology with the combination of traditional testing methods to realize testing of such devices.
This kind of testing can be divided into two situations:
A) as shown in Figure 2, solid line, non-boundary scan input device connected with the edge connector, output and DSP chips. Fault diagnosis using the software, the digital I / O modules produce a stable excitation vector, excitation vector through the edge connector anyone to the non-boundary scan devices, the response vector generated by the boundary-scan devices connected to it (DSP chip) to get through boundary-scan access to the serial output for the response vector and display. According to the working characteristics of the device under test can be analyzed theoretically expected response vector, the vector response obtained compared with the expected response vector, if the comparison results to differ, indicating possible functional device failure.
B) as shown in Figure 2, dotted line, non-boundary scan devices connected to the input and DSP chip, the output is connected with the edge connector. Use of boundary scan test software, test stimulus vectors were related to pin serial shift (with non-boundary scan devices connected to the pin) of the boundary-scan unit, and drive to the pin, the test stimulus into the device under test, the response vector generated by the edge connector from the digital I / O modules to acquire, read by the observation of fault diagnosis software. According to the working characteristics of the device under test can be analyzed theoretically expected response vector, the vector response obtained compared with the expected response vector, if the comparison results to differ, indicating possible functional device failure.
2 Test system components Hardware test system shown in Figure 3. VXI-1394 VXI system uses an external control; zero-slot module for the IEEE1394 serial communication protocol conversion for the VXI protocols; digital I / O module type is DIOM-64, each module has 64 I / O channels, three digital I / O modules provide a total of 192 test channels used to provide incentives to the circuit board under test signal and the output signal acquisition circuit board; adapter board for testing equipment and measured the signal between the matching and to the board under test provide Power supply ; JTAG interface controller signals generated by computer algorithms and standard JTAG signals between the transmission and conversion.
Software consists of software ScanWorks boundary-scan test system, fault diagnosis software TestVee, collection procedures and test response vector output incentive program. ScanWorks for the establishment and implementation of the boundary-scan test, the main features include scan chain test, interconnect test, memory test; TestVee used to control the digital I / O module working status; response vector collection procedures and test incentive program under the output is Development of measuring the actual situation in the circuit.
3 Test validation 3.1 circuit board circuit analysis
Tested plate boundary scan chain is composed of six ADSP-21060, JTAG boundary scan test interface to meet the conditions, but the pin signal definitions and ScanWorks JTAG interface adapter system of different definitions, you must re-configure the connection before the test . The device under test SN54LS245 (D33) in the tested panel of the connections shown in Figure 4. D33 of the control pin 19 (OE) by other non-boundary scan device control, where do ground handling; control pin 1 (DIR) connected to the D36A (54LS244) of 14 feet, D36A control pin connected to the edge connector on, so take advantage of digital I / O modules through the control of its working state, to achieve the working status of the D33's control.
3.2 response vector collection procedures and testing procedures for the development of export incentives
System provided by ScanWorks Macro language programming. Macro language by a compiler and a parser component, access to source code and the compiler generates an executable program and the output parser to obtain an executable program and perform. To DSP chip BSDL (Boundary Scan Description Language) file based on the response vector acquisition program input pin (INPUT) scanning unit programming, using the SAMPLE command for data collection; test stimulus output procedure output pin (OUT -PUT) scanning unit programming, using the EXTEST instruction to achieve excitation output. SN54LS245 data communication direction control for simultaneous testing of two connections, so DAT0-DAT7 separate response vector collection and testing of incentive program to send programming. To note, six DSP shared data bus, must be 6 DSP's DAT0-DAT7 pin to do the same operation, so as not to conflict with the bus signal.
3.3 Test verification 1) boundary-scan chain test Link test is normal for other boundary-scan test basis, so the link must be boundary-scan test. Connected properly tested board JTAG port, BSDL file associated with ScanWorks into the establishment of the boundary scan chain, and perform link test operation. Tested, the link works properly.
2) functional tests Determine the working state according to D33, as long as all "0" and all "1" There is enough excitation signal detection device A and B communication.
