A PLL can be implemented discretely using an integrated clock IC or a Voltage-Controlled Crystal Oscillator (VCXO), phase detector, and loop filter. A discrete solution is preferable when the lowest possible jitter and best possible phase noise are required. In some applications, processors or ASICs integrate the phase detector and charge pump within the IC so that only a VCXO and external loop filter are required.
However, there are multiple disadvantages with a discrete PLL solution. A discrete PLL requires analog design expertise and is sensitive to board-level noise, so special care must be taken in the design and PCB layout. In addition, a discrete PLL typically provides a single output frequency. If the design's frequency requirements change, a separate VCXO must be sourced. In some applications, multiple VCXOs are required to generate all of the required frequencies in the application, increasing BOM complexity. To address these shortcomings, dual, quad, and even any-rate I2C-programmable VCXOs like Silicon Lab's Si571 are available now to address multi-rate applications by replacing multiple discrete VCXOs with a single device.
An alternate approach is to use a jitter attenuating clock multiplier IC, which integrates PLL circuitry on-chip. The clock multiplier maintains lock to the reference clock, filters unwanted jitter and generates a multiplied frequency output clock for the transmitter. Special care must be taken in clock multiplier IC selection, as all clock multipliers are not created equal. For high speed serial data transmission applications, only the highest performance clock multiplier ICs provide the jitter performance necessary to meet the end application requirements. The key specification is maximum jitter generation as opposed to typical jitter generation. A clock multiplier that specifies maximum jitter best enables the hardware designer to allocate a jitter budget among the data path and timing components in the board and ensure there is sufficient margin under all conditions. Also, check the loop bandwidth options available on the clock multiplier IC. If jitter attenuation of the reference clock is required, then oftentimes the loop bandwidth must be 1 kHz or less. Lastly, confirm the clock multiplier IC supports all required frequency plans. An example of a frequency-agile clock multiplier that provides jitter attenuation and any-rate frequency synthesis is the Silicon Labs Si5319.
Lastly, a clock solution is preferable to a discrete solution when system-level clock functions are required. An example of this is hitless switching between input clocks, in which the clock monitors the quality of a primary reference clock and switches to a secondary reference upon detection of an alarm condition on the primary clock. Another popular system-level clock requirement is holdover, in which the clock continues to generate a stable output clock in the absence of a valid reference clock. Clock generators are available from multiple suppliers that address these system-level requirements.
Picking the right clock or oscillator for an upcoming design can be greatly simplified by following the guidelines listed above. Silicon Laboratories offers a broad range of jitter attenuating clock multipliers, clock generators, clock buffers, XOs, and VCXOs to meet customers' unique timing requirements.
