subject: New deep sub-micron technology design current sense amplifier - the electronics industry [print this page] New deep sub-micron technology design current sense amplifier - the electronics industry
Extensive use of Semiconductor Memory has been considerable development. Semiconductor memory performance will directly affect the system performance in speed and so on. Therefore, the design of high-speed storage of the memory it can become IC Design of a hotspot.
Speed of memory depends on memory access time. Main memory access time is the signal from the address data signal input to the output of the delay experienced in general by the address input buffers, decoders, memory cell, sense amplifier, the output buffer delay joint decision. Therefore, to reduce memory access time, there are two ways: First, to reduce the signal from the address strobe input to the word line delay, due to the internal decoder and other circuits in the form of relatively fixed, reducing in this way delay is relatively limited; the other is to reduce the word line from the data output strobe delay experienced, it can improve the sensitivity amplifier designs. Visible, high-performance sense amplifier design for improved memory performance is critical.
Sensitive amplifier's purpose was to zoom through a bit of online reading small signal changes in the data storage unit. Can generally be divided into current-sense amplifier and voltage-sensitive amplifier two. As the current sense amplifier input current directly detect changes in voltage-sensitive amplifiers can overcome a slow, low operating voltage and reduction of small-signal voltage gain of defects, the current sense amplifier by more and more attention.
With the same general sense amplifier, current sense amplifier of the work can be divided into two processes: first, pre-charging process, namely the bit line (BitLine) parasitic Capacitance To charge, so back to high, writing to prepare for the next time; second amplification process that amplifies the signal on the bit line treatment, in order to read the data stored in memory cells. This article is based on two processes, to design a new type of current sense amplifier. The amplifier pre-charge circuit can be used over an extended period (pre-charge cycle or less) to maintain the charge current at a higher value, thus reducing the pre-charge time; the same time using two amplifier amplifies the signal on the bit lines to ensure gain, speed requirements.
1 The basic structure of the current sense amplifier
Figure 1 shows the basic structure for the current sense amplifier. Where: I c Is the memory cell current; I r Is the reference current; REF is the output node; I bias Is the circuit bias current. I c By the memory cell stores information decision, when the stored information "1", I c For large current; when stored information is "0" when I c Small current; I r Value between I c Large and small electric current. REF node output voltage:
The formula: r out The output node REF in the small signal resistance. When I c I r Time, M 2 Will be in cutoff, the output voltage will be pulled Power supply Voltage V DD ; I c I r Time, M 2 Will be in the linear region, the output value will be close to 0 V.
2 new current sense amplifier Current sense amplifier as shown in Figure 1 is simple, but there are also many shortcomings, such as Power supply Voltage is not low enough, pre-charge current is small, and low slew rate. In this regard, [7] proposed a pre-controlled constant current charging circuit to improve the reading speed of the circuit, this circuit has the advantage through an inverter to achieve closure on the pre-charging circuit to ensure bit line voltage would not get impact of high store information. However, the simulation found that removing the structure of pre-charge after the inverter, by adjusting the charging circuit Transistor Parameters, the incumbent line voltage does not affect the stored information can be reached under the same fast read speed. On this basis, using GSMC0.18 m process to design a new type of current sense amplifier, shown in Figure 2. In this circuit, M 3 , M 4 , M 7 , M 8 , M 9 And the current source Ibiasl constitute the pre-charging circuit. Where M 7 , M 8 , M 9 And I biasl Mainly used to generate M 3 Gate bias V REF ; M 3 , M 4 , And M 5 For the mirror structure used to generate pre-charge current. I c And C 1 Structural simulation of parallel storage unit, this approach can effectively simulate the storage unit, but also improve the simulation efficiency, which Ic is reading the memory cell current, C 1 Is the bit line parasitic capacitance. M 10 , M 11 , M 12 , M 13 And I bias2 , I bias3 Constitute the first stage of two-stage amplifier is a differential amplifier. Differential amplifier input signals are the nodes and the BL node REF voltage. The differential amplifier using a folding mirror load, without increasing the power supply case can effectively improve the gain. The second stage amplifier for the inverter chain. This chain structure and function of the inverter can be achieved with a single inverter, but with a single inverter will lead to a higher dimension, thus significantly increasing the parasitic capacitance to reduce speed. Comprehensive consideration of size, speed and other factors, the structure of this chain has more advantages.
3 Simulation results Figure 2, when the memory cells store information as "1", I c To 13 A; memory cells store information as "0" when, Ic = 6 A. Ir as the reference current, its value is between 6 A and 13 A between, set to 10.5 A. Set C 1 To 1 pF, I bias1 = I bias2 = I bias3 = 16 A (see [6]). Shanghai Grace 0.18 m process used in the simulation under HSpice.
Figure 3 for the sense amplifier at 1.8V supply voltage and room temperature stored information "1" to enlarge the simulation graph, the abscissa is time, vertical axis is the voltage at the output node Sout. The simulation results show that, at room temperature (27 ) to read "1" response time of 13ns (In this article, all the simulation is started from 0ns), the output voltage of power supply voltage, slew rate greater. This shows that the current sense amplifier at room temperature case can be quickly and accurately read the stored information "1."
Figure 4 for the sense amplifier at 1.8V supply voltage at room temperature on the stored information "0" to enlarge the simulation graphics. The simulation results show that the output voltage changes slightly, but in the process are lower than the output voltage of 0.1V, both in the low range. This shows that the current sensitive
