subject: Ti To Promote The Ieee 1149.7 Technology Standards Development And Certification [print this page] Recently announced that it will work to promote the IEEE1149.7 standard approved. IEEE1149.7 is a new two-pin test and debug interface standard that can halve the number of pins IEEE1149.1 technology to enable designers to easily test and debug complex digital circuitry, multiple CPU and application software products, such as mobile and handheld communication devices.
IEEE1149.7 is widely spread, has been in use 20 years of IEEE1149.1 (JTAG) standard supporting the expansion and extension. Which as a port to connect embedded systems to meet new standards for the system development process device manufacturing, testing and software development needs, is expected to be approved in early 2009. In addition to maintaining compatibility with IEEE1149.1 addition, the new standards which also significantly improved debugging capabilities, and greatly reduces SoC pin-count requirements. In addition, the new standard conditions will power to achieve standardized, simplified and more Chip Stacked die module and component manufacturing, and to transmit meter data.
Since most of current systems are integrated over IC , And often has a more stringent size requirements, so by reducing the number of pins and traces will help designers to achieve product miniaturization goals and provide additional functionality pin and / or lower package cost. Set aside the relative IEEE1149.1 standard four pin, IEEE1149.7 only two pins will be able to handle the clock, control and data input and output. No longer the need for additional pins, lower pin-count configurations simplify stacked-die can significantly reduce the cost to configure and to promote the development of small-scale products. IEEE1149.7 IEEE1149.1 also with existing products and IP compatibility, so that designers do not incur additional costs in the case of a smooth transition.
New IEEE1149.7 standard IEEE1149.1 powerful extension framework to fully meet the SoC design challenge facing many, such as multi-core card scanning device performance, Power supply Domain, all devices connected topologies and background data transmission. In order to improve the performance of multi-core applications, new standards can reduce the scan chain using chip-level bypass mechanism, can greatly improve the debugging experience. For power-sensitive applications, especially in terms of handheld devices, IEEE1149.7 shutdown mode provides four can Board And chip testing and applications debugging for the engineers to help. By introducing the star topology to complement the standard serial topology, designers can easily manage multi-chip architecture, because the physical connection between devices has been greatly simplified. Background data transfer for sending data to provide an industry standard instrument approach, thereby increasing the visibility SoC devices.
Original JTAG test technology for the development of important enabling technologies, new standards and further develop the TI IEEE1149.7 a wide range of scanning technology advantage. In IEEE1149.1 standard, TI pioneered scan-based simulation and XDS series emulators technology, through direct communication with the processor chip to realize the function of all non-interventional visualization, thus significantly reducing the cost and difficulty of debugging. For IEEE1149.7, TI full advantage of the compatibility of its products in the technology and experience advantage in reducing pin count while providing new features, while not affect the current system based on IEEE1149.1 run. IEEE1149.7 standard is expected to be approved first quarter of 2009.
Ti To Promote The Ieee 1149.7 Technology Standards Development And Certification
