High-quality Voltage-controlled Crystal Oscillator (vcxo)

Managing phase noise and jitter in these high-performance applications is a necessity

. Often, a jitter attenuating clock IC or discrete phase-locked loop (PLL) is used to produce low jitter clocks. A traditional PLL architecture is comprised of a phase frequency detector (PFD), loop filter (LF) and voltage-controlled oscillator (VCO). Often the PLL filter is implemented using discrete components. One of the more challenging elements in designing with high-performance PLLs is how to choose the "right" loop bandwidth for a given application. As with many engineering challenges, this is a tradeoff decision that has to be made at the application level.

PLL output jitter is dominated by two sources: transferred reference noise and internal VCO noise. Reference noise sources include jitter generated by the reference timing source, PCB noise coupling and power supply noise. VCO noise sources include loop filter components, VCO amplifier components and power supply noise.

A jitter attenuating PLL can be used to filter noise from the input clock and produce a low jitter output clock. Reducing the loop filter bandwidth increases the amount of jitter attenuation on the reference clock, transferring less jitter from the input to the output. If the reference clock has a significant amount of jitter, using a low PLL bandwidth to filter this noise is typically recommended. However, it is not always advantageous to use a very low PLL bandwidth. The chief reason for this is that the relative contribution of VCO noise to a PLL's output jitter increases as the loop bandwidth decreases. Unless the PLL has a very low noise VCO, the impact of using a low PLL bandwidth can have the detrimental effect of actually increasing the output clock jitter. Therein lies the tradeoff decision. The PLL bandwidth needs to be set to minimize both VCO and reference jitter. Since the reference clock jitter can vary from application to application, this is a decision that needs to be made independently on each design.

A discrete PLL built using a high-quality voltage-controlled crystal oscillator (VCXO) may be used in this situation; however, the design is still sensitive to power supply switching noise, PCB noise coupling and noise introduced by the discrete loop filter components. Another option is to use a clock IC with an internal VCO, but these devices typically require external loop filter components that are sensitive to external noise sources. The interface between a PLL's loop filter and its VCO is one of the most noise-sensitive nodes in a PLL design. Noise that enters a PLL through its external loop filter components will be present on the VCO's input and will be multiplied by the VCO's gain factor, increasing the VCO noise and subsequently, the PLL noise in the design.

Solutions using discrete loop filters also increase PLL design and layout complexity. PLL stability needs to be calculated for each unique frequency plan + loop bandwidth combination to ensure there is sufficient phase margin in the design. Special PCB layout techniques such as employing guard rings around the loop filter components to provide isolation and minimize leakage current are used in some high-performance PLL designs. Since most traditional high-performance clock ICs require multiple, isolated power planes, the loop filter layout considerations add further complexity to the PCB design.

Using the Si5317 for In-Circuit Jitter Optimization

The Si5317 is a low-cost, high-performance jitter attenuating clock based on Silicon Labs' proven 3rd generation DSPLL technology. The device can accept a noisy reference clock at any frequency from 1 to 710 MHz and provide two ultra-low jitter (0.3 ps rms, 12 kHz to 20 MHz) output clocks at the same frequency. The device operating frequency is set using control pins, such that no microprocessor intervention is required. In addition, the device includes a fully integrated, digitally-controlled loop filter. Through simple pin control, hardware designers can pick the optimum loop filter value from up to 8 settings ranging from 60 Hz to 8.4 kHz, making it very easy to manage the tradeoff between transferred jitter and generated jitter and hence optimize jitter performance at the application level. This low cost, pin-controlled device can be added to any clock path and digitally tuned to produce the lowest possible output jitter, simplifying design in jitter sensitive applications.

by: Chris Bartik

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